This invention relates to an apparatus for reproducing information which have been recorded with high density and, in particular, to an apparatus for improving a follow-up performance and an information detecting performance.
Recently, it is required to process a large quantity of information with the rapid development in multi-media. Following this, requirements are also being made for a storage device having a large capacity for recording the information.
In order to meet this requirement, a recording density should be enhanced to increase a recording capacity of an optical disk devise or a HDD device as well as to reduce an error rate and to ensure the reliability.
Meanwhile, a reproducing system called xe2x80x9cPRML (Partial Response Maximum Likelihood)xe2x80x9d is popularly utilized for a file device because this system ensures a high reproducing performance for a high-density recording/reproducing waveform having a low resolution.
Herein, it is to be noted that the PRML system is structured by combining a partial response waveform equalization with a maximum likelihood detection.
It is well known to detect the maximum likelihood after correcting the reproducing waveform by equalizing the waveform in order to maximize a characteristic to a maximum likelihood detector considering a reproducing channel into account.
The PRML system is disclosed in, for example, a preprints of ITE ""94:1994 ITE Annual Convention, pages 287-288, titled xe2x80x9cA PRML System on the Optical Video Disk Recorderxe2x80x9d by S. Itoi, et al.
When the information recorded with the high density is reproduced in the optical disk and the magnetic disk, inter-symbol interference becomes large and the reproducing amplitude will be lowered.
Followingly, SNR (signal to noise ratio) becomes small in the magnetic disk while CNR (carrier to noise ratio) of a high frequency component of a readout signal becomes small in the optical disk. As a result, an error rate of a detected information will inevitably be increased.
In the maximum likelihood system, the information is detected by utilizing the characteristic of the reproducing channel having the predetermined state transfer.
The information is selected so as to minimize a root mean square of an error among all time series patterns considered from the characteristic of the reproducing channel for amplitude information series having the quantum bit number of about 8 bits inputted to the detector.
Thereby the information can be detected with a lower error rate even when the SNR or CNR is small.
It is difficult to perform the above-mentioned process with an actual circuit from the viewpoints concerning a circuit scale and an operation speed. Normally the above-mentioned process is realized by gradually selecting paths using algorithms called xe2x80x9cViterbi algorithmsxe2x80x9d. Herein, the Viterbi-algorithms are disclosed in a paper, for example, IEEE Transaction on Communications Technology, VOL. COM-19, No. 5, October 1971, pages 751-772.
In this case, the Viterbi detector and a digital circuit group connected afterward are synchronous circuits and therefore require a synchronous clock signal.
Generally, the clock signal is produced from the readout signal itself. However, the readout signal of the disk device slightly changes in accordance with the rotation jitter of a spindle or disk tilts A clock extracting circuit called PLL (Phase Locked Loop) is required in order to deal with the above-mentioned change.
In the case where the Viterbi detector is used, a stationary phase error is generated in the structure of the conventional analog PLL circuit and the PRML detector, and the error rate raises. In this viewpoint, a phase synchronous loop is generally structured by carrying out a phase comparison using a sample data (namely, a digital data) after an analog-digital conversion (A/D conversion).
For example, the above-mentioned PLL circuit is disclosed in Japanese Unexamined patent Publication (JP-A) No. Hei. 8-321140 or Japanese Unexamined patent Publication (JP-A) No. Hei. 9-204740.
In the PLL circuit disclosed in the above Japanese Unexamined Patent Publication (JP-A) No. Hei. 8-321140, an output of a loop filter (LPF; low path filter) is converted into an analog signal by the use of a D/A converter (DAC), and is supplied to a voltage control oscillator (VCO) of an analog system in order to generate a PLL clock.
In this event, it is difficult to structure the PLL circuit having the same grade of the performance because the analog VCO circuit has a large characteristic difference.
In contrast, disclosure has been made about a reproducing method in which an A/D conversion is carried out by the use of a system clock that is not synchronized with a channel clock of a readout signal, and a sample series having a desired phase is re-generated by an interpolation circuit.
By using the above-mentioned method, an entire reproducing system including the PLL circuit can be digitized.
Further, suggestion has been made about an automatic equalizing method or an adaptive equalizing method as techniques for enhancing a detecting performance by adaptively correcting deterioration of the signal with time.
For example, disclosure has been made about an continuous-type of adaptive equalizing algorithms in a paper by Hirosi Inose and Hiroshi Miyagawa, titled xe2x80x9cImprovement of PCM communicationxe2x80x9d pp. 148-184, and in particular, xe2x80x9cZero Forcing methodxe2x80x9d, xe2x80x9cMean Square methodxe2x80x9d and xe2x80x9cModified Zero Forcing methodxe2x80x9d are generally used. Such an adaptive equalizing technique has an advantageous effect because an initial adjustment of the device is not necessary.
The conventional type of a circuit for realizing the adaptive equalization includes a plurality of multipliers and integrators which as a result leads to a serious problem from the viewpoint of a circuit scale.
However, this problem has been almost resolved with the recent development of the semiconductor processing technique.
As mentioned above, the readout signal recorded with the high density is deteriorated in SNR by the affect of the inter-symbol interference. Consequently, more excellent follow-up performance can be obtained in PLL by correcting the frequency characteristic by the equalizer.
Two kinds of structures are known depending upon the arrangement of the equalizer, each of which has both the advantages and disadvantages.
A first structure is the most generally used structure, Namely, after the equalization is carried out by the use of the analog equalizer, the A/D conversion is performed to conduct the PLL operation. In first structure, it is difficult to automatically adjust the equalizing characteristic.
Therefore, the first structure can not cope with the characteristic change of the readout signal caused by the deterioration of the head, the mechanism, and the medium with time and the operating environment condition. A wide margin should preliminarily be assigned for the signal detecting system in advance.
In contrast, a second structure is illustrated in FIG. 1. Specifically, a digital equalizer 2 is inserted between an output of an A/D converter 1 given with a readout signal and a PLL circuit (including a phase comparator 41, LPF 42, DAC 44, and VCO 45) in the adaptive equalizer.
The adaptive equalizer is provided with a tap coefficient controller 6 which automatically correct the coefficient of the equalizer 2 by the use of the information before and after the equalization.
However, the numbers of taps should be increased to enhance the equalizing performance in the second structure. This increases the output delay.
Moreover, the pipeline of the circuit is required for the multipliers (not shown) in the equalizer 2 in order to perform the operation at a high speed. This also increases the output delay. As a result, the delay due to the equalizer 2 often exceeds ten stages.
In the meantime, the system adaptively follows for the inputted signal in the second structure. Therefore, the second structure is resistant to the deterioration with time and any operating environment.
However, the loop delay of PLL is increased and is damaged with respect to the follow-up characteristic in the second structure because the equalizer with the long output delay is additionally provided thereto.
It is therefore an object of this invention to provide a digital PLL circuit which follows a change with time with a short loop delay and a wide margin.
It is another object of this invention to provide an information detecting apparatus which includes a digital PLL circuit which follows a change with time with a short loop delay and a wide margin, and an equalizer which automatically follows a channel characteristic suitable for a Viterbi detection.
It is further another object of this invention to provide to an optical disk apparatus which has a digital PLL circuit which follows a change with time with a short loop delay and a wide margin and capable of enhancing reliability of the apparatus.
In an information detecting circuit according to this invention, an AID converter samples a reproducing signal with a frequency higher than a channel clock of the reproducing signal.
An equalizer equalizes an output from the A/D converter as an A/D converting information.
A first interpolation circuit generates an interpolating value from an output value series of the equalizer.
A delay circuit delays the A/D converting information with a delay quantity equivalent to an output delay quantity of the equalizer and produces the delayed information.
A second interpolation circuit generates an interpolating value from an output value series of the delay circuit.
An interpolating position generating circuit produces an interpolating position information for generating an interpolating value synchronized in phase with the channel clock of the readout signal from an output of the first interpolation circuit and supplies the interpolating position information into the first interpolation circuit and the second interpolation circuit.
A binary encoder converts the output of the first interpolation circuit into a binary code and produces a reproducing data series
A tap coefficient controller generates a tap coefficient from an interpolating value output of the first interpolation circuit and an interpolating value output of the second interpolation circuit.
A rate correcting circuit converts the tap coefficient produced from the tap coefficient controller for the equalizer.
With such a structure, the tap coefficient converted for the equalizer by the rate correcting circuit is fed-back to the equalizer.
The tap coefficient produced from the tap coefficient controller may be directly supplied to the equalizer without passing the rate correcting circuit.
Each of the first and second interpolation circuits may produce the interpolating value based upon a signal of one sample clock or a plurality of sample clocks proceeding an inputted present signal value and the interpolating position information by linearly interpolating or interpolating with higher degree.
The interpolating position generating circuit may include a phase comparator which converts an input information into a phase information, a low pass filter which is given an output of the phase comparator, and a frequency converting circuit which generates the interpolating position information on the basis of a frequency information as output of the low pass filter.
The frequency converting circuit may include means for producing an interpolating position signal having a sawtooth waveform and having a slope corresponding to a deviation quantity of the frequency, and means for producing a timing control signal for halting an operation of the circuit in a portion where the interpolating position signal becomes discontinuous.
The rate correcting circuit may produce a tap coefficient obtained by correcting the tap coefficient value produced from the tap coefficient controller with one or more degree of a timing difference between the channel clock and the sampling clock.
The binary encoder may comprise a Viterbi detector.
In an information detecting circuit according to this invention, an A/D converter samples a reproducing signal with a frequency higher than a channel clock of the reproducing signal.
A first equalizer equalizes an output from the A/D converter as an A/D converting information.
A first interpolation circuit generates an interpolating value from an output value series of the first equalizer.
A delay circuit delays the A/D converting information with a delay quantity equivalent to an output delay quantity of the first equalizer and produces the delayed information.
A second interpolation circuit generates an interpolating value from an output value series of the delay circuit.
A second equalizer equalizes the A/D converting information.
A third interpolation circuit generates an interpolating value from an output value series of the second equalizer.
An interpolating position generating circuit produces an interpolating position information for generating an interpolating value synchronized in phase with the channel clock of the reproducing signal from an output of the first interpolation circuit and supplies the interpolating position information into the first interpolation circuit, the second interpolation circuit, and the third interpolation circuit.
A first tap coefficient controller generates a tap coefficient from an interpolating value output of the first interpolation circuit and an interpolating value output of the second interpolation circuit.
A first rate correcting circuit converts the tap coefficient produced from the first tap coefficient controller for the first equalizer.
A second tap coefficient controller generates a tap coefficient from an interpolating value output of the second interpolation circuit and an interpolating value output of the third interpolation circuit.
A second rate correcting circuit converts the tap coefficient produced from the second tap coefficient controller for the second equalizer.
A binary encoder converts the output of the third interpolation circuit into a binary code and produces a reproducing data series.
With this structure, the tap coefficient produced from the first rate correcting circuit is fed-back into the first equalizer, and the tap coefficient produced from the second rate correcting circuit is fed-back into the second equalizer.
In an information detecting circuit according to this invention, an A/D converter samples a readout signal with a frequency higher than a channel clock of the readout signal.
A first equalizer equalizes an output from the A/D converter as an A/D converting information.
A first interpolation circuit generates an interpolating value from an output value series of the first equalizer.
A delay circuit delays the A/D converting information with a delay quantity equivalent to an output delay quantity to the first equalizer and produces the delayed information.
A second interpolation circuit generates an interpolating value from an output value series of the delay circuit.
A second equalizer equalizes the A/D converting information.
A third interpolation circuit generates an interpolating value from an output value series of the second equalizer.
An interpolating position generating circuit produces an interpolating position information for generating an interpolating value synchronized in phase with the channel clock of the readout signal from an output of the first interpolation circuit and supplies the interpolating position information into the first interpolation circuit, the second interpolation circuit and the third interpolation circuit.
A selector selects an output of the first interpolation circuit and an output of the third interpolation circuit in accordance with an inputted equalizing selection signal.
A tap coefficient controller is variable in an equalizing system in accordance with the equalizing selection signal and is given with an output of the selector and an output of the second interpolation circuit to produce a tap coefficient.
A rate correcting circuit converts the tap coefficient produced from the tap coefficient controller for the first and second equalizers.
First and second registers select and control so as to produce or hold an output value from the rate correcting circuit in accordance with the equalizing selection signal.
A binary encoder converts the output of the third interpolation circuit into a binary code and produces a reproducing data series.
With such a structure, the tap coefficients produced from the first and second resistors are fed-back into the first and second equalizers, respectively.
In an information detecting circuit according to this invention, an A/D converter samples a readout signal with a predetermined sample rate.
An equalizer equalizes an output from the A/D converter as an A/D converting information.
A first interpolation circuit generates an interpolating value from an output value series of the equalizer.
A delay circuit delays the A/D converting information with a delay quantity equivalent to an output delay quantity of the equalizer and produces the delayed information.
A second interpolation circuit generates an interpolating value from an output value series of the delay circuit.
An interpolating position generating circuit produces an interpolating position information for generating an interpolating value synchronized in phase with the channel clock of the readout signal from an output of the first interpolation circuit and supplies the interpolating position information into the first interpolation circuit and the second interpolation circuit.
A binary encoder converts the output to the first interpolation circuit into a binary code and produces a reproducing data series.
A tap coefficient controller generates a tap coefficient from an interpolating value output of the first interpolation circuit and an interpolating value output of the second interpolation circuit.
With this structure, the tap coefficient produced from the tap coefficient controller is directly fed-back to the equalizer.
In a reproducing apparatus according to this invention, an A/D converter A/D-converts a readout signal with a sampling clock of a frequency higher than a channel clock and produces the converted signal.
An equalizer equalizes a digital output from the ND converter with the same sampling clock as the A/D converter.
A first interpolation circuit re-samples a digital equalizing output of the equalizer on the basis of the interpolating position signal and produces an interpolating signal.
A correcting position generating circuit includes a phase comparator given with an interpolating signal of the first interpolation circuit, a loop filter, and a frequency converting circuit so as to constitute a phase synchronizing loop and produces an interpolating position signal synchronized in phase with a channel clock of the reproducing signal from the frequency converting circuit to supply into an input terminal of the interpolating position signal of the first interpolation circuit.
A second interpolation circuit re-samples an output signal of the A/D converter delayed with a delay quantity corresponding to a signal delay quantity of the equalizer by a delay circuit and produces the interpolating signal.
A tap coefficient controller is given with an interpolating position signal from the interpolating position generating circuit as an interpolating position signal of the second interpolation circuit and is given with an interpolating signal output of the first interpolation circuit and an interpolating signal output of the second interpolation circuit and produces a tap coefficient.
A rate correcting circuit converts the tap coefficient produced from the tap coefficient controller to supply into the equalizer.
A binary encoder converts the output of the first interpolation circuit into a binary code and produces a reproducing data series.
More specifically, in this invention, the reproducing signal is converted by the A/D converter into the digital signal with the sampling clock having the frequency higher than the channel clock and the output of the A/D converter is equalized by the equalizer in digital with the same sampling clock.
The sampling is carried out from the output of the equalizer by the use of the PLL circuit (see Japanese Unexamined Patent Publication (JP-A) No. Hei. 10-27435).
Further, the output of the A/D converter is delayed with the same quantity as the equalizer, and is sampled by the second interpolation circuit. It is to be noted here that the interpolating position information produced from the PLL circuit is used as the interpolating position information of the second interpolation circuit.
The interpolating information before and after the equalization (the input and output signals of the equalizer) are given to the tap coefficient controller to generate the temporary tap coefficient.
The temporary tap coefficient is converted into the operation rate of the equalizer by the rate correcting circuit, and is fed-back to the equalizer.
The interpolating output from the interpolation circuit supplied with the output of the equalizer is given to the binary encoder to be produced as the reproducing date series.
In this invention, the adaptive equalizer may be divided into two systems and may include two systems of the tap coefficient controller and the rate correcting circuit.
Alternatively, the adaptive equalizer may be divided into two systems, and the tap coefficient controller and the rate correcting circuit may be selected or switched as desired.
Moreover, when the sampling clock is near the channel clock in the information detecting circuit of this invention, the tap coefficient produced from the tap coefficient controller may be directly supplied into the equalizer without passing the rate correcting circuit.